Field of the Invention
The invention relates to a method for fabricating an integrated semiconductor memory having memory cells with vertical transistors, which are formed at webs of a semiconductor substrate, and to such an integrated semiconductor memory.
Dynamic integrated semiconductor memories have a cell array with a multiplicity of memory cells each having a storage capacitor (a trench capacitor or a stacked capacitor) and a selection transistor in each case. In order to increase the memory cell density on a semiconductor substrate, vertical transistors are desirable as selection transistors for scaling reasons. In the case of a vertical field-effect transistor (MOSFETs; metal oxide semiconductor field-effect transistor), the channel region runs perpendicularly to the substrate surface.
The vertical selection transistors are often introduced within the trenches for the storage capacitors extending deep into the substrate. In this case, the selection transistors are disposed in an upper region of the trenches and connected to one another parallel to the substrate surface by word lines and bit lines.
In a less widely used configuration of a semiconductor memory, the vertical transistors are disposed outside the trenches, to be precise at webs, that is to say vertical pillars of the substrate material, which are formed by patterning the substrate surface. The patterning gives rise to a two-dimensional configuration of webs that are isolated from one another by trenches in the semiconductor substrate. Each web serves to form a respective selection transistor and is disposed laterally beside the trench of a storage capacitor. An outdiffusion of a doped material that is conductively connected to the inner electrode of the capacitor is produced at one of the four sidewalls of the web. A lower source/drain electrode is thus formed. A gate electrode in the form of a cladding running around all four sidewalls of the web is formed above the lower source/drain electrode. The gate electrode is formed after the production of a gate oxide layer by a conductive material being deposited conformally and isotropically onto the semiconductor substrate, which has been covered with the gate oxide layer and patterned to form webs, and subsequently being etched back anisotropically in a direction perpendicular to the substrate surface, for example by dry etching (RIE; reactive ion etching). This results in a gate electrode that is in the form of a spacer and surrounds an individual web. In the course of the anisotropic etching-back, during which the top side of the web is protected by a first insulation layer, upper regions of the sidewalls of the web are uncovered. The upper source/drain implantations are later introduced in the upper, uncovered region of the webs by a preferably angled implantation. A vertical selection transistor is thus produced in each web.
The selection transistors formed in this way are connected to one another by bit lines and word lines. Gate electrodes are connected to one another by the word lines. Since the gate electrodes are in the form of a spacer having a small layer thickness at the sidewalls of the webs, it is difficult to make contact with them. The gate electrodes that are in the form of spacers and are to be connected by the word lines are situated in a lower region of the sidewalls of the webs. In the course of the gate electrodes being contact-connected by the word lines, it is necessary to bridge a large height difference. At the same time, it is necessary to prevent the substrate material in the upper region of the webs or the bit lines from being contact-connected in the course of the contact-connection of the gate electrodes. Such critical contact-connection can often only be realized with additional patternings, i.e. lithography steps for forming the contacts, and is also problematic because the gate electrodes to be contact-connected have a small layer thickness.
It is accordingly an object of the invention to provide an integrated semiconductor memory and a fabrication method that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which a semiconductor memory of the above-described configuration can be fabricated without the aid of additional lithographic patterning. Moreover, in the course of the contact-connection of the gate electrodes, the intention is to prevent inadvertent contact-connection of substrate material in the webs above the gate electrode or of bit lines.
Furthermore, the object of the present invention is to provide a semiconductor memory which can be fabricated in this way without additional lithographic patterning and without the risk of a short circuit between the gate electrodes and the substrate material or bit lines.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating an integrated semiconductor memory having memory cells with vertical transistors. The method includes the steps of providing a semiconductor substrate, depositing a first insulation layer on the semiconductor substrate, and patterning the semiconductor substrate for producing a configuration of elongate webs extending principally in a first direction and formed from a material of the semiconductor substrate and of the first insulation layer. The elongate webs are laterally isolated from one another by trenches formed in the semiconductor substrate during the patterning. A gate oxide layer is then conformally deposited and gate electrodes are produced running around the elongate webs and disposed at a level of a lower region of sidewalls of the webs on the gate oxide layer. The trenches are filled with a first insulating material, and bit lines are formed above the elongate webs. The bit lines cross the elongate webs perpendicularly to the first direction and are conductively connected to top sides of the elongate webs. At least the top sides of the bit lines are covered with a second insulation layer. A second insulating material is deposited and further trenches are etched for forming word lines. The further trenches run parallel to the first direction, and the gate electrodes are uncovered at least in an upper region due to the etching. An isotropic, conformal deposition process is performed for forming a third insulation layer having a thickness less than a layer thickness of the gate electrodes on the gate oxide layer. The third insulation layer is anisotropic etched perpendicularly to a surface of the semiconductor substrate, thereby uncovering top sides of the gate electrodes. Then, word lines are produced running above the bit lines over the elongate webs parallel to the first direction and making contact with uncovered top sides of the gate electrodes.
According to the invention, an insulation layer which is thinner than the peripheral gate electrodes is produced, so that the gate electrodes project laterally beyond that region of the insulation layer which covers the sidewall above the gate electrodes. This layer thickness difference in the lateral direction enables the gate electrodes to be contact-connected exclusively from their smaller dimension, even though the sidewalls of the spacers are covered by the third insulation layer.
The etching of the third insulation layer directed perpendicularly to the substrate surface does not attack sidewalls of the webs above the gate electrodes and sidewalls of bit lines, but does potentially attack their top sides. However, the latter are protected, according to the invention, by the first and second insulation layers, thus enabling selective uncovering exclusively of the gate electrodes. The gate electrodes can be contact-connected there by the word lines running above the webs and the bit lines. The top sides of the webs and of the bit lines, by contrast, still remain protected.
The method according to the invention has the advantage that it can be combined with a folded bit line concept, in which a memory cell is provided only at every second crossover point between a word line and a bit line; the peripheral spacers that are contact-connected on their top side can be contact-connected without giving rise to a short circuit to the passing bit lines running over them. The method according to the invention and the semiconductor circuit thereby fabricated thus combine the advantages of the folded bit line concept with those of the surrounding gate transistors. Moreover, the word lines connected to the spacers have a sufficiently low electrical resistance. Furthermore, there is no need for additional lithographic patterning (for instance for contact holes) for connecting the transistors to the bit lines.
In a preferred embodiment, it is provided that, the gate oxide layer is covered by the third insulation layer at the sidewalls of the webs above the peripheral gate electrodes. The uncovering of the gate oxide layer at an upper region of the sidewalls of the webs as a consequence of the anisotropic spacer etching-back of the peripheral gate electrodes cannot later lead to an electrical influencing of the upper source/drain electrodes through the gate oxide layer or even short circuits with the word lines since the third insulation layer insulates the two structures from one another.
Therefore, only the peripheral gate electrodes are contact-connected during the formation of the word lines.
It is preferably provided that the first, second and third insulation layers are composed of the same material, and that the layer thicknesses of the first and second insulation layers are chosen to be large enough that the top sides of the semiconductor substrate in the webs and the bit lines remain covered during the etching-back. All three insulation layers are preferably produced on a nitride, preferably made of silicon nitride. If identical materials are chosen, the insulation layers cannot be etched selectively with respect to one another. When the third insulation layer is etched back anisotropically from above, the top sides of the first and second insulation layers are also attacked as soon as the third insulation layer has been etched through. A sufficient layer thickness of the first and second insulation layers prevents uncovering of the bit lines and of the substrate material in the webs at this stage.
It may be provided that the height of the bit lines is chosen to be greater than the layer thickness of the first insulation layer. In this case, the third insulation layer is also deposited on uncovered sidewalls of the bit lines and remains there as protection against an electrical influencing of the upper source/drain potential by the subsequently deposited word line.
It is preferably provided that the gate electrodes running around the webs are formed by an electrically conductive layer being deposited conformally and etched back anisotropically perpendicularly to the surface of the semiconductor substrate, the sidewalls of the webs thereby being uncovered in an upper region of the webs. The application of the spacer technique for forming the peripheral gate electrodes, in conjunction with the smaller layer thickness of the third insulation layer with respect to the gate electrodes, enables contact-connection only of the layer thickness of the gate electrodes that projects beyond the third insulation layer on the gate electrode top side by the word lines.
Bit lines and word lines are preferably produced using the damascene technique. In particular, it is provided that the bit lines are filled in accordance with the damascene technique by filling trenches formed in an insulating material with a conductive material. In the course of this technique, first an insulating layer is deposited over the whole area and trenches for the interconnect to be formed are etched into the insulating layer. The interconnect is subsequently introduced by a conductive layer being deposited over the whole area and then being subjected to chemical mechanical planarization for example.
To facilitate the contact-connection of the top sides of the webs, it is provided that, in order to produce the bit lines, the first insulation layer is etched through to the semiconductor substrate. Dedicated contact holes for the bit lines are not necessary in this case.
In the context of the overall process for fabricating an integrated semiconductor memory, it is provided that, storage capacitors are formed, between which the webs are disposed laterally. Equally, it is provided that, source/drain electrodes are implanted into the sidewalls of the webs above the peripheral gate electrodes.
The lower source/drain electrodes are fabricated by outdiffusion of a buried doped region that proceeds from the inner capacitor electrode. A memory cell is completed in this way.
The object on which the invention is based is furthermore achieved by an integrated semiconductor memory with memory cells with vertical transistors. The semiconductor memory contains a semiconductor substrate having trenches formed therein defining webs having sidewalls and a top-side formed between the trenches, the trenches isolating the webs from each other. A first insulation layer is disposed on the top-side of the webs. An insulating material fills the trenches. A gate oxide layer covers the sidewalls of the webs and gate electrodes run around the webs, disposed on the gate oxide layer and have top sides. The top sides of the gate electrodes are disposed to be deeper than an interface between a material of the semiconductor substrate and the first insulation layer. A second insulation layer is disposed on the gate electrodes and the webs. Word lines are formed above the webs. The word lines make contact with the top sides of the gate electrodes and are isolated from the sidewalls of the webs and sidewalls of the gate electrodes by the second insulation layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor memory and a fabrication method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.